| COURSE NUMBER |
NAME OF THE COURSE |
COURSE OFFERED |
SESSIONS
(x 4 HRS.) |
| A0 |
Introduction to Modelsim ( I ) |
YES |
6 |
| A1 |
Introduction to VHDL and VLSI design ( I ) |
YES |
8 |
| A1.1 |
Introduction to VERILOG and VLSI design ( I ) |
YES |
8 |
| A2 |
Introduction to VHDL and VLSI design ( I I) |
YES |
8 |
| A2.1 |
Introduction to VERILOG and VLSI design ( I I) |
YES |
8 |
| A3 |
Matrix Keyboard Controller |
YES |
4 |
| A4 |
Generation of digital FM signals using FSK modulation |
YES |
8 |
| A5 |
Interface logic and implementation of NRF 2401 Bluetooth |
NO |
|
| A6 |
PWM robotic motor controller and implementation |
YES |
4 |
| A7 |
Priority interrupt controller (8259) |
YES |
8 |
| A8 |
Direct memory access(DMA) (8237) controller,implemented in DRAM control logic |
YES |
|
| A9 |
DRAM controller |
NO |
|
| A10 |
Generation of Sine wave with programmable voltage and frequency |
YES |
8 |
| A11 |
Bus Controller |
NO |
|
| A12 |
Fixed point CPU |
N0 |
|
| A13 |
Floating point CPU |
N0 |
|
| A14 |
FIFO Buffers |
YES |
4 |
| A15 |
A to D converter interface logic |
YES |
4 |
| A16 |
DSP Components - IIR,FIR filters |
YES |
10 |
| A17 |
3 phase IGBT sine wave inverter controller |
YES |
10 |
| A18 |
3 phase IGBT square wave inverter controller |
YES |
6 |
| A19 |
3 phase SCR converter controller |
YES |
10 |
| A20 |
Uni-Directional Shaft Encoder interface logic |
YES |
4 |
| A21 |
16 Segment x 8 LED display controller |
YES |
4 |
| A22 |
Controller for LCD VGA display (320 x 240) pixels resolution |
YES |
10 |
| A23 |
Logic for inerfacing ports and peripherals to a CPU |
YES |
4 |
| A24 |
Data scrambling and unscrambling using scrambling codes |
NO |
|
| A25 |
Positive and Negative edge Debouncing for variable Frequency noise |
YES |
4 |
| A26 |
Design of Serial Port (UART) |
YES |
6 |
| A27 |
Real Time Clock and Calendar(RTCC) and understanding the Millennium Bug |
YES |
4 |
| A28 |
Bi-Directional Shaft Encoder interface logic |
YES |
6 |
| A29 |
8051-Based Embedded VLSI Design |
YES |
2 |
| A30 |
Cordic Algorithm |
YES |
2 |
| A31 |
USB Port Design |
YES |
2 |
| A32 |
USB Architecture |
YES |
2 |
| A33 |
Fast Fourier Transformation(FFT) |
YES |
5 |
| A34 |
Phase Lock Loop(PLL) |
YES |
4 |
| A35 |
BPSK RF Demodulator |
YES |
4 |
| A36 |
I2C Master Controller |
YES |
4 |
| A37 |
CRC Genrator |
YES |
2 |
| A38 |
Parity Checker |
YES |
2 |
| A39 |
Integer Sequential Math Algorithm |
YES |
2 |
| A40 |
Floating Point Sequential Math Algorithm |
YES |
2 |
| A41 |
Veterbi Decoder |
YES |
6 |
