Associated with CDAC-ATC, Mumbai.
IP Cores >> Power
IP Cores
 
DSP
Interface
Math
Power
Sequential
Storage
Peripheral
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FEATURES

  • All designs are synchronous to a single system clock
  • All critical inputs feature digital filtering for noise immunity
  • All designs are parametric and may be customized by user
  • All designs made in VHDL and are portable across device families and vendors
 

SNO DESCRIPTION
POW1 PWM CONTROLLER
POW2 CONTROLLER FOR SINGLE PHASE SCR CONVERTERS