Associated with CDAC-ATC, Mumbai.
IP Cores >> Math
IP Cores
 
DSP
Interface
Math
Power
Sequential
Storage
Peripheral
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FEATURES

  • All designs are synchronous to a single system clock
  • All critical inputs feature digital filtering for noise immunity
  • All designs are parametric and may be customized by user
  • All designs made in VHDL and are portable across device families and vendors

SNO DESCRIPTION
MAT1 ARRAY DIVIDER
MAT2 ARRAY MULTIPLIER
MAT3 BLOCK MEMORY MULTIPLIER
MAT4 COMPLEX MULTIPLIER
MAT5 SEQUENTIAL MULTIPLIER