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FEATURES
- All designs are synchronous to a single system clock
- All critical inputs feature digital filtering for noise immunity
- All designs are parametric and may be customized by user
- All designs made in VHDL and are portable across device families and vendors
| SNO |
DESCRIPTION |
| INT1 |
CRC GENERATOR |
| INT2 |
DOUBLE BUFFERED WRITE INTERFACE |
| INT3 |
DOUBLE BUFFERED READ INTERFACE |
| INT4 |
DEBOUNCE |
| INT5 |
IP TO IP INTERFACE |
| INT6 |
GENERIC MEMORY / PORT ADDRESS DECODER |
| INT7 |
PARITY GENERATOR |
| INT8 |
STATE GENERATOR |
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