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COURSE A41: VETERBI DECODER
USES
Used in RF communication for decoding the data at the receiver end.
PREREQUISITES
Course - A1 or A1.1: Introduction to VHDL / Verilog
CONTENTS
The designing of VETERBI DECODER includes following steps:
- Designing a 16-bit deserialiser for 8 bit i/p data.
- Designing the ROM LUT.
- Control logic.
- Designing the 8-bit serializer for o/p data.
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