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COURSE A40: FLOATING PONIT SEQUENTIAL MATH ALGORITHM
USES
- Used in a host of DSP applications
- The ALU of a floating point CPU.
PREREQUISITES
Course - A1 or A1.1: Introduction to VHDL / Verilog
CONTENTS
- Understanding of Microsoft real no and IEEE real no format and difference between them.
- Designing the control and interface logic.
- Design sequential adder, Subtracter, multiplier and divider modules.
- Normalization.
- Alignment.
- Overflow and Underflow.
- Carry generation.
- Integer to floating point and floating point to integer conversion.
- Students will download the design onto an FPGA and observe the demodulated output.
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