System Automation Group

Associated with CDAC-ATC, Mumbai.

Training >> Training Courses >> VHDL >> A26

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The above VLSI components
will be designed in VHDL and simulated on the MAXPLUS+2
software from ALTERA inc. The design will then be implemented on the VLSI design kit.

COURSE A26: SERIAL PORT (UART)

USES

Bi-directional, full duplex communication between two or more microprocessor based systems.

PREREQUISITES

        Course-A1. Introduction to VHDL and VLSI design (I)

CONTENTS

        1. Interface logic for 8/16 bit CPUs
        2. Generating the 16 X Baud rate clock.
        3. Debouncing and synchronizing the I/P signals
        4. Generating the Tx and Rx baud
        5. Logic for error free detection of Start, Stop and Parity bits.
        6. Design of Serial In Parallel Out (SIPO) and Parallel In Serial Out (PISO) shift registers