Course-A1. Introduction to VHDL and VLSI design (I)

CONTENTS

        1. Parametric Designing – Generic and Generate Statement
        2. Use of internal memory - Dual Port / Single Port ROM/RAM, Synchronous/Asynchronous
        3. Multidimensional Array - Constrained & Unconstrained
        4. Resolution Functions for unconstrained multidimensional arrays
        5. Multichip project and Simulation
        6. Design of User Defined Functions
        7. Testbenches
        8. Text I/O
        9. Attributes
      10. Configuration 
      11. Package Bodies 
      12. Function Overloading Projects Implemented on an actual FPGA during the Course Parametric designing of

        1. Mux
        2. Encoder
        3. Decoder
        4. Priority Encoder
        5. Half Adder/Full Adder/4-bit Adder
        6. Comparator
        7. Counter
        8. Shift Register