System Automation Group

Associated with CDAC-ATC, Mumbai.

Training >> Training Courses >> VHDL >> A14

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The above VLSI components
will be designed in VHDL and simulated on the MAXPLUS+2
software from ALTERA inc. The design will then be implemented on the VLSI
design kit in an A to D converter application and as a CPU pre-fetch que

COURSE A14: FIFO (FIRST IN FIRST OUT) BUFFER

USES

To improve data throughput it finds use in:-
1. Pre-fetdh que in microprocessors, A to D converters, UART (serial ports), FIR,IIR filters

PREREQUISITES

        Course-A1. Introduction to VHDL and VLSI design (I)

CONTENTS

        1. Understanding how a FIFO buffer works.
        2. Generating a register file of specified depth.
        3. Generating Que read and write signals
        4. Generating and decoding the Top Of Que address.
        5. Reading and writing to the Que ie filling & depleting it
        6. Generating Que status data (level,full/empty)