In embedded systems, as the control center.

PREREQUISITES

        Course-A1. Introduction to VHDL and VLSI design (I)
        Course A14. FIFO (First In First Oout) buffer


CONTENTS


        1. Instruction design.
        2. Opcode decoder.
        3. Register design and register control logic (RCL).
        4. Effective address unit (EAU).
        5. Bus control logic (BCL).
        6. Instruction que.
        7. Stack design.
        8. Timing and control logic
        9. Arithmetic Logic Unit (ALU) 
      10. Wait state generator 
      11. Bus controller 
      12. Clock generator 
The above VLSI components will be designed in VHDL, each will be designed and simulated on the MAXPLUS+2 software from ALTERA inc and implemented on the VLSI design kit.

SPECIFICATIONS

DATA BUS WIDTH	32 bit
ADDRESS BUS WIDTH	20 bit
PRE-FETCH QUE	6 words deep
BUS STATES	INTEL 80286 compatible
FLOATING POINT UNIT	Optimised for 32 bit (REAL 4)
MEMORY	Segmented
ADDRESSING MODES	Direct, Indirect, Register, Immediate
INSTRUCTION SET	Similar to intel 80286,80287

REGISTERS

REG	NAME	USE	SIZE (BITS)
CL[]	Count register	Count, general purpose	16
AL[]	general purpose	general purpose	23
AH[]	general purpose	general purpose	9
AX[]	general purpose	general purpose	32
BL[]	general purpose	general purpose	23
BH[]	general purpose	general purpose	9
BX[]	general purpose	general purpose	32
DL[]	general purpose	general purpose	23
DH[]	general purpose	general purpose	9
DX[]	general purpose	general purpose	32
BP[]	Base Pointer	index, general purpose	16
SI[]	Source index	index, general purpose	16
DI[]	Destination index	index, general purpose	16
SP[]	Stack pointer	stack pointer, general purpose	16
DS[]	Data segment	data segment	16
ES[]	Extra segment	extra segment, general purpose	16
CS[]	Code segment	code segment	16
IP[]	Instruction pointer	instruction pointer	16

INSTRUCTION SET -Similar to intel 80286,80287

NAME	FUNCTION	NAME	FUNCTION
ADD	Integer ADD	JL	Jump if less than
AND	AND source w/ detination and replace destination	JG	Jump if greater than
CLI	Clear interrupt flag	LOOP	Loop back to label till CL[] register is zero & decrement CL[]
CLD	Clear direction flag	MOV	Move source to destination
CALL	Call function	MVP	Port I/O
CMP	Compare source and destination	MUL	Integer multiplication
DIV	Integer divisio	MOVS	Move string
DEC	Decrement by one	NOT	Binary inversion
FADD	Unnormalised floating point addition	NOP	No operation
FSUB	Unnormalised floating point subtraction	OR	OR source with destination and replace destination
FDIV	Normalised floating point division	POPF	POP flags register from stack
FADN	Normalised floating point addition	PSHF	PUSH flags register onto stack
FSBN	Normalised floating point subtraction	PUSH	PUSH operand onto stack
FMUL	Normalised floating point multiplication	POP	POP operand from stack
FTOI	Float to integer conversion	REP	Repeat next instruction till contents of CL[] register become zero
INT	Soft interrupt	RET	Return from non interrupt routine
IRET	Return from interrupt service routine	ES:	Segment override prefix(select extra segment register)
INC	Increment by One	STI	Set interrupt flag
ITOF	Integer to float conversion	STD	Set direction flag
JMP	Jump to label	SUB	Integer subtration
JZ	Jump if zero flag is set	SHL	Shift left one bit or multiple bits (depending on usage)
JNZ	Jump if zero flag is reset	SHR	Shift right one bit or multiple bits (depending on usage)
JLE	Jump if less than or equal to	TEST	AND source with destination but do not replace
JGE	Jump if greater than or equal to