Associated with CDAC-ATC, Mumbai. Home | VC++ | VLSI Kits | Training | IP Cores | SOPC Cores | Turnkey Projects | About Us Training >> Training Courses >> VHDL >> A1.1 Training   • Training Courses     • VHDL     • ORCAD     • AUTOCAD     • PIC Microcontroller     • Assembly Language     • Linux & VC     • Others     • Process Logic Controller • Training Facilities   Project work is given on the basis of modules taught during the course and are implemented on our VLSI TRAINER KIT. COURSE A1.1: INTRODUCTION TO VERILOG AND VLSI DESIGN (I) PREREQUISITES 1. Knowledge of digital electronics.  CONTENTS 1. Introduction to Graphic Editor 2. Introduction to PLD's HDL's Digital design with Verilog.  3. Hierarchical Modeling concept Design methodologies Modules Component declaration Data types 4. Modules and Ports Module declaration Port declaration Connecting port to external signals 5. Data Flow modeling Continuous assignments Expressions, operators and operands 6. Behavioral modeling Structured procedure Procedural assignment Conditional statements Multiway branching Loops Sequential and parallel blocks Generate blocks 7. Tasks and Functions Task declaration and invocation Function declaration and invocation 8. Clock Configuration Guidelines 9. Metastability 10. Projects basic gates 4:1 mux Half adder/ Full adder T-ff Encoder (4:2,8:3) Decoder (2:4,3:8) Priority Encoder(4:2,8:3) Counter Shift Register © 2008 System Automation Group Home | VC++ | VLSI Kits | Training | IP Cores | SOPC Cores | Turnkey Projects | About Us