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COURSE A0: INTRODUCTION TO MODELSIM ( I )
PREREQUISITES
Knowledge of VHDL/Verilog/ System Verilog
CONTENTS
1. Introduction to Modelsim
- Basic simulation flow
- Creating the working library
- Compiling your design
- Running the simulation
2. ModelSim projects
- Creating a new project
- Adding objects to the project
- Changing compile order (VHDL)
- Compiling and loading a design
- Organizing projects with folders
3. Working with multiple libraries
- Creating the project
- Linking to the resource library
4. Functional Simulation in Modelsim
5. Timing Simulation in Modelsim
- Extracting the .vho file with Quartus
- Generating the .sdf file with Quartus
6. Multichip simulation
- Compiling the node designs
- Combining the node designs to a top hierarchy design
- Simulation the top hierarchy design
7. Projects Implemented on an actual FPGA during the Course
- Mux(2:1, 4:1, 8:1, 16:1)
- Encoder(4:2, 8:3)
- Decoder(2:4, 3:8)
- Priority Encoder(4:2, 8:3)
- Half Adder / Full Adder / 4 – bit Adder
- Comparator(1 – Bit, 4 – Bit)
- Counter
- Shift Register
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